An integrated circuit (IC) design may be developed using a method or system such as electronic design automation (EDA), computer aided design (CAD), and other IC design software. Such methods and systems may be used to generate a circuit pattern database from the IC design. The circuit pattern database includes data representing a plurality of layouts for various layers of the IC. Data in the circuit pattern database may be used to determine layouts for a plurality of reticles. A layout of a reticle generally includes a plurality of shapes (polygons) that define features in a pattern on the reticle. Each reticle is used to fabricate one of the various layers of the IC. The layers of the IC may include, for example, a junction pattern in a semiconductor substrate, a gate dielectric pattern, a gate electrode pattern, a contact pattern in an inter-level dielectric, or an interconnect pattern on a metallization layer.
Fabricating semiconductor devices, such as logic and memory devices, typically includes processing a substrate like a semiconductor wafer using a large number of semiconductor fabrication processes to form various features and multiple levels of the semiconductor devices. For example, lithography is a semiconductor fabrication process that involves transferring a pattern from a reticle to a resist arranged on a semiconductor wafer. Additional examples of semiconductor fabrication processes include, but are not limited to, chemical-mechanical polishing, etch, deposition, and ion implantation. Multiple semiconductor devices may be fabricated in an arrangement on a single semiconductor wafer and then separated into individual semiconductor devices.
Inspection methods are used at various steps during a semiconductor manufacturing process to detect defects on wafers to promote higher yield in the manufacturing process. As the dimensions of semiconductor devices decrease, inspection becomes even more important to the successful manufacture of acceptable semiconductor devices because smaller defects may cause the devices to fail.
Optical inspection of a semiconductor wafer during manufacturing is generally a slow, manual process. Defect teams at semiconductor fabrication plant (fabs) usually use optical based tools for wafer inspection, but typically perform scanning electron microscope (SEM) review of defects for verification. Thus, for every layer inspected on an optical inspection tool, a sampled population of defects is then reviewed on an SEM tool. Manual classification of the reviewed defects is tedious and time-consuming. Fabs use many automatic detection and classification schemes to save the time and effort involved in defect classification. However, the automatic detection and classification schemes have limitations and are not a replacement for a human classification. One aspect of this flow is automatic defect detection, which involves subtraction of reference and defect sites to locate the defect. A previous technique involved subtracting the whole images within certain field of view (FOV) with the defect image. Besides requiring large computation power, this technique increased the probability of including a nuisance or instances of multiple, non-important defects. This subtraction technique also is non-selective and will have reduced defect of interest (DOI) selectivity for SEM detection.
Also when semiconductor fabs use optical inspector tools for monitoring defects on the wafer, the inspection recipe on the optical inspector tool is optimized for DOI. If an automated SEM detection and classification system is used for defects coming from an optical inspector source, a nuisance on the wafer could have an adverse impact. In such a case, though the optical inspector tool found the DOI, it might get reported into a nuisance bin by the automated SEM detection and classification system. A nuisance also can be reported in a defect bin.
Previous methods for SEM automatic wafer detection and classification that are used for reviewing defects from an optical inspection source do not have an effective mechanism to control the detection of prominent nuisance present on the wafer. These methods have at least the following limitations. First, these methods lack region-specific (e.g., care area) defect selectivity. Second, these methods have higher throughput costs for detection because these methods process complete SEM images within FOV for detection even if part of FOV is not an area of interest. Third, these methods have misdetection problems that lead to higher misclassification. Fourth, SEM detection optimization is cumbersome because current algorithms are forced to deal with all the pixels in the FOV, many of which contribute to misdetection problems while being of no interest.
Methods for integrating design into a review tool, such as an SEM, do not yet solve the problems and drawbacks of the previous methods. Therefore, what is needed is an improved defect detection technique with a review tool, and, more particularly, and improved electron beam defect detection technique.